1. Field of the Invention
The present invention relates to a method for reducing the phase noise introduced in the resynchronization by justification of digital signals used in data and/or voice transmission. The invention also relates to devices for implementing such a method.
2. Description of the Related Art
In the transmission of numerical data, the justification method is widely used for resynchronizing a plesiochronous stream. The justification method is characterized by its use of a local clock.
In particular, this method is used in numerical multiplexing devices. An international standard (CCITT, e.g. recommendations G707-G709 for synchronous multiplexers) establishes the characteristics of tributary data streams, the characteristics of aggregated data streams, the structures of frames and the position and the number of justification digits for each level of the consolidated multiplexing hierarchies.
The traditional structure of a resynchronizer using justification includes an elastic memory into which data is written at the clock rate associated with the plesiochronous stream, and from which data read out by the local clock, to which is appended a frame that includes digits of the so-called justification or filling. The use (or non-use) of filling digits as information or redundancy allows one to achieve the resynchronization between the remote and local clocking.
There are three types of justification: positive, negative, or positive-negative justification, according to whether the filling digits are normally used as information, not usually used as information, or both types of justification digits are present in each frame.
Conventionally, the use of justification digits is established once each frame, based on a comparison between the digital signal representing the phase difference between the local and remote clock and a fixed threshold (in the case of positive or negative justification) or two thresholds (in the case of positive-negative justification).
It is well known from the literature (e.g. D. L. Dutweiler, "Waiting Time Jitter", Bell Syst. Tech. J. Vol. 51, January 1972, identified the following as D1), that operating justification in the above mentioned manner introduces phase noise in the resynchronized data stream, that is clearly evident at the moment of desynchronization by PLL ("Phase Locked Loop") and that depends on the frequency of the data stream, on the local clock frequency and on the frame structure, through the value of the filling ratio .rho., defined as: ##EQU1##
In particular, the phase noise is particularly high when the filling factor reaches values near to a rational number p/q, where p and q are positive integer numbers.
The worst case is positive-negative justification, in which the value of filling ratio is near zero and the phase noise can have an amplitude of 1 UIpp ("Unit of peak-peak pulse").
The international standard establishes the limit of the phase noise which can be present in the desynchronized stream (CCITT, e.g. recomm. G783 for the synchronous multiplexers) and, in the case of plesiochronous multiplexers, it establishes the frame structures, and these limits must be respected when operating the justification by the above-mentioned conventional method.
The case of synchronous hierarchy, whose standardization process is actually the execution phase, clearly shows that the structures of the standardized frames do not allow the conventional fulfillment of the justification techniques, as the introduced phase noise can be too high.
In fact, the so-called "mappings" of plesiochronous tributaries in VCs ("Virtual Containers") of the frame STM-1 ("Synchronous Transport Module of Level 1"), forming the base frame of the synchronous hierarchy, cause filling ratios particularly unfavorable with regard to the phase noise introduced in the signal, and in some circumstances, they cause the worst case of positive-negative justification, with the filling ratio being close to zero.
The literature has recently proposed (e.g. Choi, "Waiting Time Jitter Reduction", IEEE Trans. on Comm., Vol. 37, no. 11, November 1989, identified in the following as D2) different techniques for reducing the phase noise introduced by the resynchronization process in the case of positive-negative justification. These techniques are all based on the hypothesis that it is possible to reduce the phase noise by artificially modifying the value of the filling ratio by utilizing a procedure for generating the phase comparing signal which is more complex than the procedure employed in conventional techniques.
Using the proposed techniques, it is possible to reduce the phase noise of resynchronization following the positive-negative justification within the limits established in international standardization, using circuits of increased complexity for performing the phase comparison. But the solution offered by these techniques has a limit and a drawback.
The limit is that the literature does not disclose techniques suitable for reducing the phase noise in the case of purely positive or negative justification, where the filling ratio is "unfavorable" in the above-mentioned meaning.
The drawback is that the reduction value is limited by the presence of "peaks" in phase noise obtained after the desynchronization towards the detuning of the plesiochronous stream with respect to the normal frequency value.
To better understand the above problems, reference is made to FIG. 1, which shows the result of a plesiochronous tributary at 2,048 Mb/sec mapped by the positive-negative justification in a VC-12 ("Virtual Container with level 1,2") of a frame STM-1. The ordinate indicates the peak-peak amplitude App of the phase noise or jitter, resulting from the desynchronization made by PLL, while the abscissas represents the detuning D.sub.freq between the real frequency of the plesiochronous flow and the nominal frequency, normalized at the frame frequency.
It is possible to cause the peaks to remain included within the standard limits, typically by the selection of a suitable value of .rho. obtained with a corresponding increase of the circuit complexity, but it is not possible to avoid completely these peaks.